Amplifying circuit, ad converter, integrated circuit, and wireless communication apparatus

ABSTRACT

An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-097191, filed on May 12, 2015, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an amplifying circuit, an AD converter, an integrated circuit, and a wireless communication apparatus.

BACKGROUND

In the related art, an amplifying circuit including a main operational amplifier and a subsidiary operational amplifier is suggested to reduce an amplification error occurring due to finite gain of an operational amplifier. In the amplifying circuit, a virtual ground voltage of the subsidiary operational amplifier is amplified and is added to an output voltage of the main operational amplifier. As a result, gain of the main operational amplifier can be improved in an equivalent manner, the amplification error can be reduced, and amplification precision of the amplifying circuit can be improved.

However, in the amplifying circuit according to the related art, the amplification error occurs due to mismatching between the main operational amplifier and the subsidiary operational amplifier caused by a manufacturing variation of a semiconductor. In the amplifying circuit according to the related art, improvement of the amplification precision is limited by the amplification error.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram illustrating an amplifying circuit according to the related art;

FIG. 2 is a circuit diagram illustrating an example of the amplifying circuit of FIG. 1;

FIG. 3 is a functional block diagram illustrating an amplifying circuit according to the related art including a main operational amplifier and a subsidiary operational amplifier;

FIG. 4 is a functional block diagram illustrating an amplifying circuit according to a first embodiment;

FIG. 5 is a circuit diagram illustrating an amplifying circuit according to a second embodiment;

FIG. 6 is a circuit diagram illustrating an amplifying circuit according to a third embodiment;

FIG. 7 is a circuit diagram illustrating an amplifying circuit according to a fourth embodiment;

FIG. 8 is a circuit diagram illustrating an amplifying circuit according to a fifth embodiment;

FIG. 9 is a circuit diagram illustrating an amplifying circuit according to a sixth embodiment;

FIG. 10 is a circuit diagram illustrating an amplifying circuit according to a seventh embodiment;

FIG. 11 is a circuit diagram illustrating an operational amplifier according to an eighth embodiment;

FIG. 12 is a functional block diagram illustrating an AD conversion circuit according to a ninth embodiment; and

FIG. 13 is a diagram illustrating a hardware configuration of a wireless communication apparatus according to a tenth embodiment.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.

An amplifying circuit according to an embodiment includes an input terminal, an output terminal, a first operational amplifier, a first input impedance element, a first feedback impedance element, a second operational amplifier, a second input impedance element, a second feedback impedance element, a third feedback impedance element, and an adder. The input terminal receives an input voltage. The output terminal outputs an output voltage. The first operational amplifier includes an inversion input terminal connected to a first node, a non-inversion input terminal, and an output terminal connected to a second node. One end of the first input impedance element is connected to the input terminal and the other end thereof is connected to the first node. One end of the first feedback impedance element is connected to the first node and the other end thereof is connected to the second node. The second operational amplifier includes an inversion input terminal connected to a third node, a non-inversion input terminal, and an output terminal connected to a fourth node. One end of the second input impedance element is connected to the input terminal and the other end thereof is connected to the third node. One end of the second feedback impedance element is connected to the third node and the other end thereof is connected to the fourth node. One end of the third feedback impedance element is connected to the first node and the other end thereof is connected to the fourth node. The adder adds an output voltage of the first operational amplifier and an output voltage of the second operational amplifier and outputs an added output voltage.

First, an amplifying circuit according to the related art will be described. FIG. 1 is a functional block diagram illustrating the amplifying circuit according to the related art. The amplifying circuit of FIG. 1 includes an input terminal T_(IN), an output terminal T_(OUT), an amplifier A, a feedback circuit β, and a subtracter SUB. The input terminal T_(IN) receives an input voltage V_(IN). The output terminal T_(OUT) outputs an output voltage V_(OUT). If gain of the amplifier A is set as A and a feedback coefficient of the feedback circuit β is set as β, the output voltage V_(OUT) of the amplifying circuit is represented by the following formula.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack & \; \\ {V_{OUT} = {\frac{1}{\beta}\left\{ {1 - \frac{1}{\beta \; A} + \left( \frac{1}{\beta \; A} \right)^{2} - \ldots}\mspace{14mu} \right\} V_{IN}}} & (1) \end{matrix}$

In the formula 1, the output voltage V_(OUT) is Taylor-expanded and is shown. Meanwhile, a first term (1/β×V_(IN)) of a right side of the formula 1 is an expectation value (design value) of the output voltage V_(OUT). Meanwhile, a portion (1/β×{−1/βA+(1/βA)²− . . . }×V_(IN)) after a second term of the right side of the formula 1 is an error voltage to an expectation value of the output voltage V_(OUT). Hereinafter, an X-th term of the right side of the formula 1 is simply referred to as the X-th term.

From the formula 1, it is known that the error voltage is inversely proportional to the gain A of the amplifier A and becomes 0 when A is infinite. However, in actuality, the gain A has a finite value. In addition, it is difficult to manufacture the amplifier A having high gain, due to miniaturzation of a semiconductor process. For this reason, in the amplifying circuit of FIG. 1, the error voltage according to the gain A is generated.

For example, in the case of β=½ and A=100, the first term of the formula 1 becomes 1/β×V_(IN)=2×V_(IN), the second term becomes −1/β²A²×V_(IN)=−0.04×V_(IN), and the third term becomes 1/β³A²×V_(IN)=0.0008×V_(IN). Therefore, if a portion after a fourth term is ignored, V_(OUT)=(2−0.04+0.0008)V_(IN)=2.0408V_(IN) is obtained. That is, in the output voltage V_(OUT), an error voltage of 2.04% is generated with respect to the expectation value.

FIG. 2 is a circuit diagram illustrating an example of the amplifying circuit of FIG. 1. An amplifying circuit of FIG. 2 includes an input terminal T_(IN), an output terminal T_(OUT), an operational amplifier OP, an input impedance element Zi, and a feedback impedance element Zf. The operational amplifier OP corresponds to the amplifier A of FIG. 1. If gain of the operational amplifier OP is set as A, impedance of the input impedance element Zi is set as Zi, and impedance of the feedback impedance element Zf is set as Zf, an output voltage V_(OUT) of the amplifying circuit is represented by the following formula.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 2} \right\rbrack & \; \\ {V_{OUT} = {{- \frac{Z_{f}}{Z_{i}}}\left\{ {1 - \frac{Z_{i} + Z_{f}}{Z_{i}A} + \left( \frac{Z_{i} + Z_{f}}{Z_{i}A} \right)^{2} - \ldots}\mspace{11mu} \right\} V_{IN}}} & (2) \end{matrix}$

Similar to the formula 1, a first term of the formula 2 is an expectation value of the output voltage V_(OUT) and a portion after a second term of the formula 2 is an error voltage to the expectation value of the output voltage V_(OUT). In addition, in the formula 2, a feedback coefficient β is Zi/Zf. From the formulas 1 and 2, it is known that the error voltage of the amplifying circuit according to the related art is inversely proportional to the gain A and an error voltage of the second term is dominant.

Therefore, in the related art, an amplifying circuit of FIG. 3 is suggested as an amplifying circuit to reduce the error voltage. FIG. 3 is a functional block diagram illustrating an amplifying circuit according to the related art including a main operational amplifier and a subsidiary operational amplifier. The amplifying circuit of FIG. 3 includes an input terminal T_(IN), an output terminal T_(OUT), amplifiers A₁ to A₃, feedback circuits β₁ and β₂, subtracters SUB, and SUB₂, and an adder AD. The amplifier A₁ is a main amplifier and the amplifiers A₂ and A₃ are subsidiary amplifiers. If gains of the amplifiers A₁ to A₃ are set as A₁ to A₃, feedback coefficients of the feedback circuits β₁ and β₂ are set as β₁ and β₂, and β₁=β₂=β is set, an output voltage V_(OUT) of the amplifying circuit is represented by the following formula.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 3} \right\rbrack & \; \\ {V_{OUT} = {\frac{1}{\beta}\left\{ {1 - {\frac{1}{\beta \; A_{1}}\left( {1 - \frac{A_{3}}{A_{2}}} \right)} - \frac{A_{3}}{\beta^{2}A_{1}A_{2}^{2}} + \ldots}\mspace{14mu} \right\} V_{IN}}} & (3) \end{matrix}$

In the formula 3, a first term is an expectation value of the output voltage V_(OUT) and a portion after a second term is an error voltage to the expectation value of the output voltage V_(OUT). As known from the formula 3, the error voltage is inversely proportional to the gain A₁. This is the same as the amplifying circuit of FIG. 1. Meanwhile, the amplifying circuit of FIG. 3 is different from the amplifying circuit of FIG. 1 in that an error voltage of the second term is removed in the case of A₂=A₃.

As described above, in the amplifying circuit of FIG. 1, the error voltage of the second term is dominant in the error voltage of the output voltage V_(OUT). For this reason, if the error voltage of the second term is removed, the entire error voltage can be reduced. For example, in the case of β=½ and A₁=A₂=A₃=100, the first term of the formula 3 becomes 1/β×V_(IN)=2×V_(IN), the second term becomes −(1/β²A₁)(1−A₃/A₂)×V_(IN)=0, and the third term becomes −A₃/β³A₁A₂ ²×V_(IN)=−0.0008×V_(IN). Therefore, if a portion after a fourth term is ignored, V_(OUT)=(2−0.0008)V_(IN)=1.9992V_(IN) is obtained. That is, an error voltage generated in the output voltage V_(OUT) of the amplifying circuit of FIG. 3 is 0.04% with respect to an expectation value. As such, the amplifying circuit of FIG. 3 can greatly reduce the error voltage, as compared with the amplifying circuit of FIG. 1.

However, in actuality, mismatching occurs in the main amplifiers A₂ and A₃, due to a manufacturing variation or an environmental variation of the semiconductor. The mismatching means that a deviation occurs in gains of the two amplifiers. For example, when A₂ and A₃ deviate by 20% and A₃/A₂=1.2 is obtained, the second term of the formula 3 becomes 0.008×V_(IN) and V_(OUT)=(2+0.008−0.0008)V_(IN)=2.0082V_(IN) is obtained. At this time, the error voltage becomes 0.41% and becomes larger than an error voltage in the case of A₂=A₃ (the case in which the mismatching does not occur) by one digit.

As such, in the amplifying circuit according to the related art illustrated in FIG. 3, the error voltage generated in the output voltage V_(OUT) increases due to the mismatching of the gains between the amplifiers.

First Embodiment

Hereinafter, an amplifying circuit according to a first embodiment will be described with reference to FIG. 4. FIG. 4 is a functional block diagram illustrating the amplifying circuit according to this embodiment. As illustrated in FIG. 4, the amplifying circuit includes an input terminal T_(IN), an output terminal T_(OUT), amplifiers A₁ and A₂, feedback circuits β₁ to β₃, subtracters SUB₁ and SUB₂, and an adder AD. The input terminal T_(IN) receives an input voltage V_(IN). The output terminal T_(OUT) outputs an output voltage V_(OUT).

The amplifier A₁ is a main amplifier of the amplifying circuit according to this embodiment. The amplifier A₁ receives an output voltage of the subtracter SUB₁. The amplifier A₁ amplifies the received voltage with predetermined gain and outputs the voltage. It is assumed that gain of the amplifier A₁ is A₁. The output voltage of the amplifier A₁ is input to the adder AD and the feedback circuit β₁. The amplifier A₁ is configured by an operational amplifier, for example.

The amplifier A₂ is a subsidiary amplifier of the amplifying circuit according to this embodiment. The amplifier A₂ receives an output voltage of the subtracter SUB₂. The amplifier A₂ amplifies the received voltage with predetermined gain and outputs the voltage. It is assumed that gain of the amplifier A₂ is A₂. The output voltage of the amplifier A₂ is input to the adder AD and the feedback circuits β₂ and β₃. The amplifier A₂ is configured by an operational amplifier, for example.

The feedback circuit β₁ receives the output voltage of the amplifier A₁. The feedback circuit β₁ feeds back a voltage according to the received voltage. It is assumed that a feedback coefficient of the feedback circuit β₁ is β₁. The voltage fed back by the feedback circuit β₁ is input to the subtracter SUB₁. The feedback circuit β₁ is configured by an impedance element such as a resistive element and a capacitative element, for example. The feedback circuit β₂ receives the output voltage of the amplifier A₂. The feedback circuit β₂ feeds back a voltage according to the received voltage. It is assumed that a feedback coefficient of the feedback circuit β₂ is β₂. The voltage fed back by the feedback circuit β₂ is input to the subtracter SUB₂. The feedback circuit β₂ is configured by an impedance element such as a resistive element and a capacitative element, for example.

The feedback circuit β₃ receives the output voltage of the amplifier A₂. The feedback circuit β₃ feeds back a voltage according to the received voltage. It is assumed that a feedback coefficient of the feedback circuit β₃ is β₃. The voltage fed back by the feedback circuit β₃ is input to the subtracter SUB₁. The feedback circuit β₃ is configured by an impedance element such as a resistive element and a capacitative element, for example.

The subtracter SUB₁ receives the input voltage V_(IN) and the voltages fed back by the feedback circuits β₁ and β₃. The subtracter SUB₁ subtracts the voltages fed back by the feedback circuits β₁ and β₃ from the input voltage V_(IN) and outputs the voltage. An output voltage of the subtracter SUB₁ is input to the amplifier A₁.

The subtracter SUB₂ receives the input voltage V_(IN) and the voltage fed back by the feedback circuit β₂. The subtracter SUB₂ subtracts the voltage fed back by the feedback circuit β₂ from the input voltage V_(IN) and outputs the voltage. An output voltage of the subtracter SUB₂ is input to the amplifier A₂.

The adder AD receives the output voltage of the amplifier A₁ and the output voltage of the amplifier A₂. The adder AD adds the output voltage of the amplifier A₁ and the output voltage of the amplifier A₂ and outputs the voltage. An output voltage of the adder AD becomes the output voltage V_(OUT) of the amplifying circuit.

If β₁=β₂=β₃=β is set, the output voltage V_(OUT) of the amplifying circuit according to this embodiment is represented by the following formula.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 4} \right\rbrack & \; \\ {V_{OUT} = {\frac{1}{\beta}\left( {1 - \frac{1}{\beta^{2}A_{1}A_{2}} + \ldots}\mspace{11mu} \right)V_{IN}}} & (4) \end{matrix}$

In the formula 4, a first term is an expectation value of the output voltage V_(OUT) and a portion after a second term is an error voltage to the expectation value of the output voltage V_(OUT). As known from the formula 4, an error voltage of the second term is inversely proportional to A₁×A₂.

For example, in the case of β=½ and A₁=A₂=100, the first term of the formula 4 becomes 1/β×V_(IN)=2×V_(IN), the second term becomes −1/β³A₁A₂×V_(IN)=−0.0008×V_(IN). Therefore, if a portion after a third term is ignored, V_(OUT)=(2−0.0008)V_(IN)=1.9992V_(IN) is obtained. That is, an error voltage generated in the output voltage V_(OUT) of the amplifying circuit according to this embodiment becomes 0.04% with respect to the expectation value. As such, similar to the amplifying circuit of FIG. 3, the amplifying circuit according to this embodiment can greatly reduce the error voltage as compared with the amplifying circuit of FIG. 1, when mismatching does not occur between the amplifiers.

Meanwhile, different from the amplifying circuit of FIG. 3, in the amplifying circuit according to this embodiment, even when the mismatching occurs between the amplifiers A₁ and A₂, the error voltage can be suppressed.

For example, when A₁ and A₂ deviate by 20% and A₁=80 and A₂=100 are obtained, the second term becomes 0.001×V_(IN). Therefore, if a portion after a third term is ignored, V_(OUT)=(2−0.001)V_(IN)=1.999V_(IN) is obtained. At this time, it is known that the error voltage is 0.05% and becomes smaller than the error voltage of the amplifying circuit of FIG. 3 by one digit. As such, in the amplifying circuit according to this embodiment, the error voltage when the mismatching occurs between the amplifiers can be greatly reduced as compared with the amplifying circuit of FIG. 3. This is because the second term of the formula 4 is inversely proportional to the square (A₁×A₂) of the gain.

As described above, the amplifying circuit according to this embodiment can suppress a dominent error voltage (error voltage of the second term) in the error voltage generated in the output voltage V_(OUT). Therefore, the input voltage V_(IN) can be amplified with high precision.

In addition, even when the mismatching of the gains occurs between the amplifiers, due to the manufacturing variation or the environmental variation of the semiconductor, the amplifying circuit according to this embodiment can reduce the error voltage and amplify the input voltage V_(IN) with high precision.

Second Embodiment

A second embodiment will be described with reference to FIG. 5. In this embodiment, an example of the amplifying circuit according to the first embodiment will be described. FIG. 5 is a circuit diagram illustrating an example of the amplifying circuit of FIG. 4.

As illustrated in FIG. 5, the amplifying circuit according to this embodiment includes an input terminal T_(IN), an output terminal T_(OUT), operational amplifiers OP₁ to OP₃, input impedance elements Zi₁₁, Zi₁₂, Zi₂₁, and Zi₂₂, and feedback impedance elements Zf₁₁, Zf₁₂, Zf₁₃, and Zf₂.

The operational amplifier OP₁ (first operational amplifier) is a main operational amplifier. An inversion input terminal (−) of the operational amplifier OP₁ is connected to a node N₁ (first node), a non-inversion input terminal (+) thereof is connected to a ground line, and an output terminal thereof is connected to a node N₂ (second node). The node N₁ is a connection point of the inversion input terminal of the operational amplifier OP₁, the input impedance element Zi₁₁, and the feedback impedance elements Zf₁₁ and Zf₁₃. The node N₂ is a connection point of the output terminal of the operational amplifier OP₁, the input impedance element Zi₂₁, and the feedback impedance element Zf₁₁. Hereinafter, “connected to the ground line” is called “grounded”. The operational amplifier OP₁ corresponds to the amplifier A₁ of FIG. 4. It is assumed that gain of the operational amplifier OP₁ is A₁.

The operational amplifier OP₂ (second operational amplifier) is a subsidiary operational amplifier. An inversion input terminal (−) of the operational amplifier OP₂ is connected to a node N₃ (third node), a non-inversion input terminal (+) thereof is grounded, and an output terminal thereof is connected to a node N₄ (fourth node). The node N₃ is a connection point of the inversion input terminal of the operational amplifier OP₂, the input impedance element Zi₁₂, and the feedback impedance element Zf₁₂. The node N₄ is a connection point of the output terminal of the operational amplifier OP₂, the input impedance element Zi₂₂, and the feedback impedance elements Zf₁₂ and Zf₁₃. The operational amplifier OP₂ corresponds to the amplifier A₂ of FIG. 4. It is assumed that gain of the operational amplifier OP₂ is A₂.

One end of the input impedance element Zi₁₁ (first input impedance element) is connected to the input terminal T_(IN) and the other end thereof is connected to the node N₁. The input voltage V_(IN) is applied to the inversion input terminal of the operational amplifier OP₁ through the input impedance element Zi₁₁. It is assumed that impedance of the input impedance element Zi₁₁ is Zi₁₁.

One end of the input impedance element Zi₁₂ (second input impedance element) is connected to the input terminal T_(IN) and the other end thereof is connected to the node N₃. The input voltage V_(IN) is applied to the inversion input terminal of the operational amplifier OP₂ through the input impedance element Zi₁₂. It is assumed that impedance of the input impedance element Zi₁₂ is Zi₁₂.

One end of the feedback impedance element Zf₁₁ (first feedback impedance element) is connected to the node N₁ and the other end thereof is connected to the node N₂. The output voltage of the operational amplifier OP₁ is fed back to the inversion input terminal of the operational amplifier OP₁ through the feedback impedance element Zf₁₁. It is assumed that impedance of the feedback impedance element Zf₁₁ is Zf₁₂.

One end of the feedback impedance element Zf₁₂ (second feedback impedance element) is connected to the node N₃ and the other end thereof is connected to the node N₄. The output voltage of the operational amplifier OP₂ is fed back to the inversion input terminal of the operational amplifier OP₂ through the feedback impedance element Zf₁₂. It is assumed that impedance of the feedback impedance element Zf₁₂ is Zf₁₂.

One end of the feedback impedance element Zf₁₃ (third feedback impedance element) is connected to the node N₁ and the other end thereof is connected to the node N₄. The output voltage of the operational amplifier OP₂ is fed back to the inversion input terminal of the operational amplifier OP₁ through the feedback impedance element Zf₁₃. It is assumed that impedance of the feedback impedance element Zf₁₃ is Zf₁₃.

An inversion input terminal (−) of the operational amplifier OP₃ (third operational amplifier) is connected to a node N₅ (fifth node), a non-inversion input terminal (+) thereof is grounded, and an output terminal thereof is connected to the output terminal T_(OUT). The node N₅ is a connection point of the inversion input terminal of the operational amplifier OP₃, the input impedance elements Zi₂₁ and Zi₂₂, and the feedback impedance element Zf₂. It is assumed that gain of the operational amplifier OP₃ is A₃.

One end of the feedback impedance element Zf₂ (fourth feedback impedance element) is connected to the node N₅ and the other end thereof is connected to the output terminal T_(OUT). The output voltage of the operational amplifier OP₃ is fed back to the inversion input terminal of the operational amplifier OP₃ through the feedback impedance element Zf₂. It is assumed that impedance of the feedback impedance element Zf₂ is Zf₂.

One end of the input impedance element Zi₂₁ (third input impedance element) is connected to the node N₂ and the other end thereof is connected to the node N₅. The output voltage of the operational amplifier OP₁ is applied to the inversion input terminal of the operational amplifier OP₃ through the input impedance element Zi₂₁. It is assumed that impedance of the input impedance element Zi₂₁ is Zi₂₁.

One end of the input impedance element Zi₂₂ (fourth input impedance element) is connected to the node N₄ and the other end thereof is connected to the node N₅. The output voltage of the operational amplifier OP₂ is applied to the inversion input terminal of the operational amplifier OP₃ through the input impedance element Zi₂₂. It is assumed that impedance of the input impedance element Zi₂₂ is Zi₂₂.

In the amplifying circuit according to this embodiment, the impedance of each impedance element is set to satisfy Zi₁₁=Zi₁₂=Zi₁, Zf₁₁=Zf₁₂=Zf₁₃=Zf₁, and Zi₂₁=Zi₂₂=Zi₂. By the above configuration, each functional configuration of the amplifying circuit of FIG. 4 is realized. In this embodiment, the adder AD is configured by the input impedance elements Zi₂₁ and Zi₂₂, the operational amplifier OP₃, and the feedback impedance element Zf₂.

When the gain A₃ is sufficiently large and Zi₂=Zf₂ is obtained, the output voltage V_(OUT) of the amplifying circuit according to this embodiment is represented by the following formula.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 5} \right\rbrack & \; \\ {V_{OUT} = {\frac{Z_{f\; 1}}{Z_{i\; 1}}\left( {1 + {\frac{1}{A_{1}A_{2}}\frac{{2Z_{i\; 1}} + {3Z_{i\; 1}Z_{f\; 1}} + Z_{f\; 1}^{2}}{Z_{i\; 1}^{2}}} + \ldots}\mspace{11mu} \right)V_{IN}}} & (5) \end{matrix}$

A first term of the formula 5 is an expectation value of the output voltage V_(OUT) and a portion after a second term of the formula 5 is an error voltage to the expectation value of the output voltage V_(OUT). As known from the formula 5, an error voltage of the second term is inversely proportional to A₁×A₂. Therefore, the same effect as the effect of the amplifying circuit of FIG. 4 is obtained by the amplifying circuit according to this embodiment.

In the amplifying circuit of FIG. 5, a feedback circuit is formed by the operational amplifier OP₃ and the feedback impedance element Zf₂. A feedback coefficient of the feedback circuit is Zi₂/Zf₂. Therefore, the output voltage V_(OUT) according to this embodiment becomes a voltage that is Zi₂/Zf₂ times larger than a voltage obtained by adding the output voltages of the operational amplifiers OP₁ and OP₂. The formula 5 shows the output voltage V_(OUT) in the case of Zi₂/Zf₂=1. However, even in the case of Zi₂/Zf₂≠1, the error voltage of the second term is inversely proportional to A₁×A₂. Therefore, the same effect as the effect of the amplifying circuit of FIG. 4 is obtained without depending on Zi₂ and Zf₂.

Third Embodiment

A third embodiment will be described with reference to FIG. 6. In this embodiment, a modification of the amplifying circuit of FIG. 5 will be described. An amplifying circuit according to this embodiment is an amplifying circuit obtained by connecting the amplifying circuits of FIG. 5 in a cascade manner. FIG. 6 is a circuit diagram illustrating the amplifying circuit according to this embodiment.

As illustrated in FIG. 6, the amplifying circuit according to this embodiment further includes output terminals T_(OUT1) and T_(OUT2), an operational amplifier OP₄, input impedance elements Zi₂₃ and Zi₂₄, and feedback impedance elements Zf₂₁, Zf₂₂, and Zf₂₃. The output terminal T_(OUT1) corresponds to the output terminal T_(OUT) of FIG. 5. The feedback impedance element Zf₂₁ corresponds to the feedback impedance element Zf₂. The other configuration is the same as the configuration of the amplifying circuit of FIG. 5. In addition, in this embodiment, an operational amplifier OP₃ configures an amplifier A₁ of an amplifying circuit of a second step and the feedback impedance element Zf₂, configures a feedback circuit β₁ of the amplifying circuit of the second step.

An inversion input terminal (−) of the operational amplifier OP₄ (fourth operational amplifier) is connected to a node N₆ (sixth node), a non-inversion input terminal (+) thereof is connected to a ground line, and an output terminal thereof is connected to the output terminal T_(OUT2). The node N₆ is a connection point of the inversion input terminal of the operational amplifier OP₄, the input impedance elements Zi₂₃ and Zi₂₄, and the feedback impedance element Zf₂₂. It is assumed that gain of the operational amplifier OP₄ is A₄.

One end of the input impedance element Zi₂₃ (fifth input impedance element) is connected to a node N₂ and the other end thereof is connected to the node N₆. An output voltage of an operational amplifier OP, is applied to the inversion input terminal of the operational amplifier OP₄ through the input impedance element Zi₂₃. It is assumed that impedance of the input impedance element Zi₂₃ is Zi₂₃.

One end of the input impedance element Zi₂₄ (sixth input impedance element) is connected to a node N₄ and the other end thereof is connected to the node N₆. An output voltage of an operational amplifier OP₂ is applied to the inversion input terminal of the operational amplifier OP₄ through the input impedance element Zi₂₄. It is assumed that impedance of the input impedance element Zi₂₄ is Zi₂₄.

One end of the feedback impedance element Zf₂₂ (fifth feedback impedance element) is connected to the node N₆ and the other end thereof is connected to the output terminal T_(OUT2). An output voltage of the operational amplifier OP₄ is fed back to the inversion input terminal of the operational amplifier OP₄ through the feedback impedance element Zf₂₂. It is assumed that impedance of the feedback impedance element Zf₂₂ is Zf₂₂.

One end of the feedback impedance element Zf₂₃ (sixth feedback impedance element) is connected to a node N₅ and the other end thereof is connected to the output terminal T_(OUT2). An output voltage of the operational amplifier OP₄ is fed back to the inversion input terminal of the operational amplifier OP₃ through the feedback impedance element Zf₂₃. It is assumed that impedance of the feedback impedance element Zf₂₃ is Zf₂₃.

In the amplifying circuit according to this embodiment, the impedance of each impedance element is set to satisfy Zi₂₃=Zi₂₄=Zi₂ and Zf₂₂=Zf₂₃=Zf₂. In the amplifying circuit according to this embodiment, the operational amplifiers OP₃ and OP₄ correspond to the amplifiers A₁ and A₂ of the amplifying circuit of the second step. In addition, the output terminals T_(OUT1) and T_(OUT2) correspond to the nodes N₂ and N₄ of the amplifying circuit of the second step.

The amplifying circuits of FIG. 5 can be connected in a cascade manner by any number of steps by alternately connecting four impedance elements (configurations corresponding to the input impedance elements Zi₂₁ to Zi₂₄) and two operational amplifiers and four feedback impedance elements (configurations corresponding to the operational amplifiers OP₃ and OP₄ and the feedback impedance elements Zf₂₁ to Zf₂₃) to rear steps of the output terminals T_(OUT1) and T_(OUT2) and connecting an adder AD to a final step. For example, an amplifying circuit in which the amplifying circuits of FIG. 5 are connected in a cascade manner in two steps is configured by connecting the adder AD to the rear steps of the output terminals T_(OUT1) and T_(OUT2).

According to this embodiment, an amplifying circuit having any amplification factor can be realized by connecting the amplifying circuits of FIG. 5 in a cascade manner by any number of steps. In addition, the amplifying circuit according to this embodiment can be applied to a filter circuit having a plurality of orders.

Fourth Embodiment

A fourth embodiment will be described with reference to FIG. 7. In this embodiment, another example of the amplifying circuit according to the first embodiment will be described. An amplifying circuit according to this embodiment includes a switched capacitor circuit and has two operation phases of a sample phase and an amplification phase. FIG. 7 is a circuit diagram illustrating the amplifying circuit according to this embodiment.

As illustrated in FIG. 7, the amplifying circuit according to this embodiment includes an input terminal T_(IN), an output terminal T_(OUT), operational amplifiers OP₁ and OP₂, sample-and-hold circuits SH₁ to SH₄, feedback capacitative elements Cf₁₁ to Cf₁₃, AD converters ADC₁ and ADC₂, and a digital adder ad. The operational amplifiers OP₁ and OP₂ are the same as the operational amplifiers OP₁ and OP₂ of FIG. 5.

The sample-and-hold circuit SH₁ (first sample-and-hold circuit) is a switched capacitor circuit and corresponds to the input impedance element Zi_(n) of FIG. 5. The sample-and-hold circuit SH₁ includes switches SW₁₁ to SW₁₃ and a sample capacitative element Ci₁₁.

One end of the switch SW₁₁ is connected to the input terminal T_(IN) and the other end thereof is connected to a node N₇ (seventh node). The node N₇ is a connection point of the switches SW₁₁ and SW₁₂ and the sample capacitative element Ci₁₁. One end of the switch SW₁₂ is connected to the node N₇ and the other end thereof is grounded. One end of the switch SW₁₃ is connected to a node N₁ and the other end thereof is grounded.

One end of the sample capacitative element Ci₁₁ is connected to the node N₇ and the other end thereof is connected to the node N₁. It is assumed that a capacity value of the sample capacitative element Ci₁₁ is Cl₁₁.

In the sample-and-hold circuit SH₁, in the sample phase, the switches SW₁₁ and SW₁₃ are turned on and the switch SW₁₂ is turned off. As a result, the input voltage V_(IN) is sampled in the sample capacitative element Ci₁₁.

In addition, in the sample-and-hold circuit SH₁, in the amplification phase, the switches SW₁₁ and SW₁₃ are turned off and the switch SW₁₂ is turned on. As a result, the input voltage V_(IN) sampled in the sample capacitative element Ci₁₁ is held.

The sample-and-hold circuit SH₂ (second sample-and-hold circuit) is a switched capacitor circuit and corresponds to the input impedance element Zi₁₂ of FIG. 5. The sample-and-hold circuit SH₂ includes switches SW₂₁ to SW₂₃ and a sample capacitative element Ci₁₂.

One end of the switch SW₂₁ is connected to the input terminal T_(IN) and the other end thereof is connected to a node N₈ (eighth node). The node N₈ is a connection point of the switches SW₂₁ and SW₂₂ and the sample capacitative element Ci₁₂. One end of the switch SW₂₂ is connected to the node N₈ and the other end thereof is grounded. One end of the switch SW₂₃ is connected to a node N₃ and the other end thereof is grounded.

One end of the sample capacitative element Ci₁₂ is connected to the node N₈ and the other end thereof is connected to the node N₃. It is assumed that a capacity value of the sample capacitative element Ci₁₂ is Ci₁₂.

In the sample-and-hold circuit SH₂, in the sample phase, the switches SW₂₁ and SW₂₃ are turned on and the switch SW₂₂ is turned off. As a result, the input voltage V_(IN) is sampled in the sample capacitative element Ci₁₂.

In addition, in the sample-and-hold circuit SH₂, in the amplification phase, the switches SW₂₁ and SW₂₃ are turned off and the switch SW₂₂ is turned on. As a result, the input voltage V_(IN) sampled in the sample capacitative element Ci₁₂ is held.

One end of the feedback capacitative element Cf₁₁ is connected to the node N₁ and the other end thereof is connected to the node N₂. The feedback capacitative element Cf₁₁ corresponds to the feedback impedance element Zf₁₁ of FIG. 5. An output voltage of the operational amplifier OP₁ is fed back to an inversion input terminal of the operational amplifier OP₁ through the feedback capacitative element Cf₁₁. It is assumed that a capacity value of the feedback capacitative element Cf₁₁ is Cf₁₁.

One end of the feedback capacitative element Cf₁₂ is connected to the node N₃ and the other end thereof is connected to the node N₄. The feedback capacitative element Cf₁₂ corresponds to the feedback impedance element Zf₁₂ of FIG. 5. An output voltage of the operational amplifier OP₂ is fed back to an inversion input terminal of the operational amplifier OP₂ through the feedback capacitative element Cf₁₂. It is assumed that a capacity value of the feedback capacitative element Cf₁₂ is Cf₁₂.

One end of the feedback capacitative element Cf₁₃ is connected to the node N₁ and the other end thereof is connected to the node N₃. The feedback capacitative element Cf₁₃ corresponds to the feedback impedance element Zf₁₃ of FIG. 5. The output voltage of the operational amplifier OP₂ is fed back to the inversion input terminal of the operational amplifier OP₁ through the feedback capacitative element Cf₁₃. It is assumed that a capacity value of the feedback capacitative element Cf₁₃ is Cf₁₃.

The sample-and-hold circuit SH₃ (third sample-and-hold circuit) is a switched capacitor circuit and includes switches SW₃₁ to SW₃₃ and a sample capacitative element Ci₂₁.

One end of the switch SW₃₁ is connected to the node N₂ and the other end thereof is connected to a node N₉ (ninth node). The node N₉ is a connection point of the switches SW₃₁ and SW₃₂ and the sample capacitative element Ci₂₁. One end of the switch SW₃₂ is connected to the node N₉ and the other end thereof is grounded. One end of the switch SW₃₃ is connected to a node N₁₀ (tenth node) and the other end thereof is grounded. The node N₁₀ is a connection point of the switch SW₃₂, the sample capacitative element Ci₂₁, and an input terminal of the AD converter ADC₁.

One end of the sample capacitative element Ci₂₁ is connected to the node N₉ and the other end thereof is connected to the node N₁₀. It is assumed that a capacity value of the sample capacitative element Ci₂₁ is Ci₂₁.

In the sample-and-hold circuit SH₃, in the amplification phase, the switches SW₃₁ and SW₃₃ are turned on and the switch SW₃₂ is turned off. As a result, the output voltage of the operational amplifier OP₁ is sampled in the sample capacitative element Ci₂₁.

In addition, in the sample-and-hold circuit SH₃, in the sample phase, the switches SW₃₁ and SW₃₃ are turned off and the switch SW₃₂ is turned on. As a result, the output voltage of the operational amplifier OP₁ sampled in the sample capacitative element Ci₂₁ is held and is input to the AD converter ADC₁.

An input terminal of the AD converter ADC₁ (first AD converter) is connected to the node N₁₀ and an output terminal thereof is connected to an input terminal of the digital adder ad. In the amplification phase, the AD converter ADC₁ receives an output voltage of the sample-and-hold circuit SH₃, executes AD conversion on the received voltage, and outputs a digital signal. The digital signal output by the AD converter ADC₁ is input to the digital adder ad.

The sample-and-hold circuit SH₄ (fourth sample-and-hold circuit) is a switched capacitor circuit and includes switches SW₄₁ to SW₄₃ and a sample capacitative element Ci₂₂.

One end of the switch SW₄₁ is connected to the node N₄ and the other end thereof is connected to a node N₁₁ (eleventh node). The node N₁₁ is a connection point of the switches SW₄₁ and SW₄₂ and the sample capacitative element Ci₂₂. One end of the switch SW₄₂ is connected to the node N₁₁ and the other end thereof is grounded. One end of the switch SW₄₃ is connected to a node N₁₂ (twelfth node) and the other end thereof is grounded. The node N₁₂ is a connection point of the switches SW₄₂, the sample capacitative element Ci₂₂, and an input terminal of the AD converter ADC₂.

One end of the sample capacitative element Ci₂₂ is connected to the node N₁₁ and the other end thereof is connected to the node N₁₂. It is assumed that a capacity value of the sample capacitative element Ci₂₂ is Ci₂₂.

In the sample-and-hold circuit SH₄, in the amplification phase, the switches SW₄₁ and SW₄₃ are turned on and the switch SW₄₂ is turned off. As a result, the output voltage of the operational amplifier OP₂ is sampled in the sample capacitative element Ci₂₂.

In addition, in the sample-and-hold circuit SH₄, in the sample phase, the switches SW₄₁ and SW₄₃ are turned off and the switch SW₄₂ is turned on. As a result, the output voltage of the operational amplifier OP₂ sampled in the sample capacitative element Ci₂₂ is held and is input to the AD converter ADC₂.

An input terminal of the AD converter ADC₂ (second AD converter) is connected to the node N₁₂ and an output terminal thereof is connected to the input terminal of the digital adder ad. In the amplification phase, the AD converter ADC₂ receives an output voltage of the sample-and-hold circuit SH₄, executes AD conversion on the received voltage, and outputs a digital signal. The digital signal output by the AD converter ADC₂ is input to the digital adder ad.

The digital adder ad receives the digital signals output by the AD converters ADC₁ and ADC₂. The digital adder ad adds the received digital signals and outputs an added digital signal. The output signal of the digital adder ad becomes the output voltage V_(OUT) in this embodiment. For this reason, in this embodiment, the output voltage V_(OUT) becomes the digital signal.

In the amplifying circuit according to this embodiment, the capacity value of each capacitative element is set to satisfy Ci₁₁=Ci₁₂ Cf₁₁=Cf₁₂=Cf₁₃=Cf₁, and Ci₂₁=Ci₂₂=Ci₂. By the above configuration, each functional configuration of the amplifying circuit of FIG. 4 is realized. In this embodiment, the adder AD is configured by the sample-and-hold circuits SH₃ and SH₄, the AD converters ADC₁ and ADC₂, and the digital adder ad.

The amplifying circuit amplifies the input voltage V_(IN) at a predetermined interval of time by repeating the sample phase and the amplification phase alternately. Here, if resolutions of the AD converters ADC₁ and ADC₂ are set infinitely, the output voltage V_(OUT) is represented by the following formula, from the law of conservation of charge.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 6} \right\rbrack & \; \\ {V_{OUT} = {\frac{C_{i\; 1}}{C_{f\; 1}}\left( {1 - \frac{2}{A_{1}A_{2}} + \ldots}\mspace{11mu} \right)V_{i\; n}}} & (6) \end{matrix}$

A first term of the formula 6 is an expectation value of the output voltage V_(OUT) and a portion after a second term of the formula 6 is an error voltage to the expectation value of the output voltage V_(OUT). As known from the formula 6, an error voltage of the second term is inversely proportional to A₁×A₂. Therefore, the same effect as the effect of the amplifying circuit of FIG. 4 is obtained by the amplifying circuit according to this embodiment.

In this embodiment, the magnitude of the input signal of the AD converter ADC₁ is smaller than the magnitude of the input signal of the AD converter ADC₂. For this reason, the resolution of the AD converter ADC₁ may be smaller than the resolution of the AD converter ADC₂.

Fifth Embodiment

A fifth embodiment will be described with reference to FIG. 8. In this embodiment, a modification of the amplifying circuit of FIG. 7 will be described. FIG. 8 is a circuit diagram illustrating an amplifying circuit according to this embodiment. As illustrated in FIG. 8, the amplifying circuit according to this embodiment includes an operational amplifier OP₃ and a feedback capacitative element Cf₂, instead of the AD converters ADC₁ and ADC₂ and the digital adder ad of FIG. 7. The other configuration is the same as the configuration of the amplifying circuit of FIG. 7.

An inversion input terminal (−) of the operational amplifier OP₃ is connected to nodes N₁₀ and N₁₂, a non-inversion input terminal (+) thereof is grounded, and an output terminal thereof is connected to an output terminal T_(OUT). It is assumed that gain of the operational amplifier OP₃ is A₃. It is assumed that the gain A₃ is sufficiently large.

One end of the feedback capacitative element Cf₂ is connected to the nodes N₁₀ and N₁₂ and the other end thereof is connected to the output terminal T_(OUT). An output voltage of the operational amplifier OP₃ is fed back to the inversion input terminal of the operational amplifier OP₃ through the feedback capacitative element Cf₂. It is assumed that a capacity value of the feedback capacitative element Cf₂ is Cf₂.

In this embodiment, an adder AD is configured by the sample-and-hold circuits SH₃ and SH₄, the operational amplifier OP₃, and the feedback capacitative element Cf₂.

In the amplifying circuit of FIG. 8, a feedback circuit is formed by the operational amplifier OP₃ and the feedback capacitative element Cf₂. A feedback coefficient of the feedback circuit is Ci₂/Cf₂. Therefore, the output voltage V_(OUT) according to this embodiment becomes a voltage that is Ci₂/Cf₂ times larger than a voltage obtained by adding the output voltages of the operational amplifiers OP₁ and OP₂. Similar to the amplifying circuit of FIG. 7, in the amplifying circuit according to this embodiment, an error voltage of a second term is inversely proportional to A₁×A₂ without depending on Ci₂ and Cf₂. Therefore, the same effect as the effect of the amplifying circuit of FIG. 4 is obtained by the amplifying circuit according to this embodiment.

Sixth Embodiment

A sixth embodiment will be described with reference to FIG. 9. In this embodiment, another modification of the amplifying circuit of FIG. 7 will be described. FIG. 9 is a circuit diagram illustrating an amplifying circuit according to this embodiment. As illustrated in FIG. 9, the amplifying circuit according to this embodiment includes a buffer circuit B and a sample-and-hold circuit SH₅, instead of the sample-and-hold circuits SH₃ and SH₄, the AD converters ADC₁ and ADC₂, and the digital adder ad of FIG. 7. The other configuration is the same as the configuration of the amplifying circuit of FIG. 7.

An input terminal of the buffer circuit B is connected to a node N₂ and an output terminal thereof is connected to one end of a switch SW₅₃. In an amplification phase, the buffer circuit B receives an output voltage of an operational amplifier OP₁, inverts the received voltage, and outputs the voltage. That is, gain of the buffer circuit B is −1.

The sample-and-hold circuit SH₅ (fifth sample-and-hold circuit) is a switched capacitor circuit and includes switches SW₅₁ to SW₅₃ and a sample capacitative element Ci₂.

One end of the switch SW₅₁ is connected to a node N₄ and the other end thereof is connected to a node N₁₃ (thirteenth node). The node N₁₃ is a connection point of the switches SW₅₁ and SW₅₂ and the sample capacitative element Ci₂. One end of the switch SW₅₂ is connected to the node N₁₃ and the other end thereof is grounded. One end of the switch SW₅₃ is connected to an output terminal of the buffer circuit B and the other end thereof is connected to an output terminal T_(OUT).

One end of the sample capacitative element Ci₂ is connected to the node N₁₃ and the other end thereof is connected to the output terminal T_(OUT). It is assumed that a capacity value of the capacitative element Ci₂ is Ci₂.

In the sample-and-hold circuit SH₅, in an amplification phase, the switches SW₅₁ and SW₅₃ are turned on and the switch SW₅₂ is turned off. As a result, an output voltage of the operational amplifier OP₂ and an output voltage of the buffer circuit B are sampled in the sample capacitative element Ci₂.

The output voltage of the buffer circuit B is obtained by inverting an output voltage of the operational amplifier OP₁. In addition, the output voltage of the buffer circuit B is input to the sample capacitative element Ci₂ from the side opposite to the input side of the output voltage of the operational amplifier OP₂. As a result, a voltage obtained by adding the output voltages of the operational amplifiers OP₁ and OP₂ is sampled in the sample capacitative element Ci₂. As such, in this embodiment, an adder AD is configured by the buffer circuit B and the sample-and-hold circuit SH₅.

In addition, in the sample-and-hold circuit SH₅, in a sample phase, the switches SW₅₁ and SW₅₃ are turned off and the switch SW₅₂ is turned on. As a result, the voltage (sum of the output voltage of the operational amplifier OP₂ and the output voltage of the buffer circuit B) sampled in the sample capacitative element Ci₂ is held and is output as an output voltage V_(OUT). As such, according to the amplifying circuit according to this embodiment, the adder AD can be configured using the buffer circuit B.

Seventh Embodiment

A seventh embodiment will be described with reference to FIG. 10. In this embodiment, a modification of the amplifying circuit of FIG. 9 will be described. FIG. 10 is a circuit diagram illustrating an amplifying circuit according to this embodiment. As illustrated in FIG. 10, the amplifying circuit according to this embodiment is obtained by changing the configuration of the amplifying circuit of FIG. 9 to a differential configuration and includes an amplifying circuit of the inversion input side and an amplifying circuit of the non-inversion input side.

The amplifying circuit (hereinafter, referred to as the “amplifying circuit P”) of the inversion input side includes an input terminal T_(INP) that receives an input voltage V_(INP) and an output terminal T_(OUTP) that outputs an output voltage V_(OUTP). The amplifying circuit (hereinafter, referred to as the “amplifying circuit M”) of the non-inversion input side includes an input terminal T_(INM) that receives an input voltage V_(INM) and an output terminal T_(OUTM) that outputs an output voltage V_(OUTM). Different from the amplifying circuit of FIG. 9, both the amplifying circuits P and M do not include a buffer circuit B.

An inversion input terminal of an operational amplifier OP₁ is connected to a node N₁ of the amplifying circuit P and a non-inversion input terminal thereof is connected to a node N₁ of the amplifying circuit M. In addition, an inversion output terminal of the operational amplifier OP₁ is connected to a node N₂ of the amplifying circuit P and a non-inversion output terminal thereof is connected to a node N₂ of the amplifying circuit M.

An inversion input terminal of an operational amplifier OP₂ is connected to a node N₃ of the amplifying circuit P and a non-inversion input terminal thereof is connected to a node N₃ of the amplifying circuit M. In addition, an inversion output terminal of the operational amplifier OP₂ is connected to a node N₄ of the amplifying circuit P and a non-inversion output terminal thereof is connected to a node N₄ of the amplifying circuit M.

In addition, in this embodiment, the node N₂ of the amplifying circuit P is connected to one end of a switch SW₅₃ of the amplifying circuit M and the node N₂ of the amplifying circuit M is connected to one end of a switch SW₅₃ of the amplifying circuit P. That is, an output voltage of the operational amplifier OP₁ of the amplifying circuit P is input to a sample capacitative element Ci₂ of the amplifying circuit M and an output voltage of the operational amplifier OP₁ of the amplifying circuit M is input to a sample capacitative element Ci₂ of the amplifying circuit P.

By such a configuration, the output voltage of the operational amplifier OP₁ can be inverted and can be input to the sample capacitative element Ci₂ of the amplifying circuit P, without using the buffer circuit B in which gain is −1. Likewise, the output voltage of the operational amplifier OP₁ can be inverted and can be input to the sample capacitative element Ci₂ of the amplifying circuit M. Therefore, in this embodiment, an adder AD is configured by a sample-and-hold circuit SH₅.

Eighth Embodiment

An eighth embodiment will be described with reference to FIG. 11. In this embodiment, an example of an operational amplifier configuring an amplifying circuit will be described. FIG. 11 is a circuit diagram illustrating the operational amplifier according to this embodiment. As illustrated in FIG. 11, the operational amplifier according to this embodiment includes transistors M₁ to M₅. Hereinafter, an inversion input terminal of the operational amplifier is called an input terminal T_(INP), a non-inversion input terminal thereof is called an input terminal T_(INM), an inversion output terminal thereof is called an output terminal T_(OUTP), and a non-inversion output terminal thereof is called an output terminal T_(OUTM). In FIG. 11, V_(DD) shows a power-supply voltage.

The transistor M₁ is a P-channel MOS transistor (hereinafter, referred to as the “PMOS”). A source terminal of the transistor M₁ is connected to a power line, a drain terminal thereof is connected to the output terminal T_(OUTP), and a gate terminal thereof is connected to a gate terminal of the transistor M₂. A bias voltage V_(BP) is applied to the gate terminal.

The transistor M₂ is a PMOS. A source terminal of the transistor M₂ is connected to a power line, a drain terminal thereof is connected to the output terminal T_(OUTM), and a gate terminal thereof is connected to the gate terminal of the transistor M₁. The bias voltage V_(BP) is applied to the gate terminal.

The transistor M₃ is an N-channel MOS transistor (hereinafter, referred to as the “NMOS”). A source terminal of the transistor M₃ is connected to a drain terminal of the transistor M₅, a drain terminal thereof is connected to the output terminal T_(OUTP), and a gate terminal thereof is connected to the input terminal T_(INP).

The transistor M₄ is an NMOS. A source terminal of the transistor M₄ is connected to a drain terminal of the transistor M₅, a drain terminal thereof is connected to the output terminal T_(OUTM), and a gate terminal thereof is connected to the input terminal T_(INM).

The transistor M₅ is an NMOS. A source terminal of the transistor M₅ is grounded, a drain terminal thereof is connected to the source terminals of the transistors M₃ and M₄, and a bias voltage V_(BN) is applied to a gate terminal thereof.

The amplifying circuit according to each embodiment described above can improve the gain of the main amplifier in an equivalent manner by connecting the main amplifier and the subsidiary amplifier. For this reason, even when the operational amplifier having the simple configuration illustrated in FIG. 11 is used as the amplifier, the input voltage V_(IN) can be amplified with high precision by suppressing an error voltage.

The operational amplifier of FIG. 11 has the differential configuration. However, the operational amplifier may have a single-phase configuration. In addition, the operational amplifier of FIG. 11 is configured by the MOS transistors. However, the operational amplifier may be configured by transistors of a different type such as bipolar transistors.

Ninth Embodiment

An AD converter according to a ninth embodiment will be described with reference to FIG. 12. FIG. 12 is a functional block diagram illustrating the AD converter according to this embodiment. The AD converter according to this embodiment includes any one of the amplifying circuits according to the first to seventh embodiments. As illustrated in FIG. 12, the AD converter includes a sampling device, an amplifier, and a quantizer.

The sampling device samples an input analog signal at a predetermined interval of time and outputs a sampled signal. The amplifier amplifies an output signal of the sampling device with predetermined gain and outputs the output signal. The quantizer quantizes the output signal of the amplifier and outputs a digital signal.

In the AD converter according to this embodiment, the amplifier is configured by any one of the amplifying circuits according to the first to seventh embodiments. In addition, a function of the sampling device may be realized by a sample-and-hold circuit SH of the amplifying circuit. An output signal V_(OUT) of the amplifying circuit becomes the output signal of the amplifier and is quantized by the quantizer.

The amplifying circuit according to each embodiment described above can improve gain of a main amplifier in an equivalent manner by connecting the main amplifier and a subsidiary amplifier. In addition, an amplification error can be suppressed from occurring due to mismatching between the main amplifier and the subsidiary amplifier. Because the AD converter according to this embodiment includes the amplifying circuit, high-precision AD conversion is enabled.

Tenth Embodiment

An integrated circuit and a wireless communication apparatus according to a tenth embodiment will be described with reference to FIG. 13. FIG. 13 is a diagram illustrating a hardware configuration of the wireless communication apparatus according to this embodiment. The hardware configuration is exemplary and various changes can be made in the hardware configuration.

As illustrated in FIG. 13, the wireless communication apparatus according to this embodiment a baseband circuit 111, an RF circuit 121, and antennas.

The baseband circuit 111 includes a control circuit 112, a transmission processing circuit 113, a reception processing circuit 114, DA converters 115 and 116, and AD converters 117 and 118. The RF circuit 121 and the baseband circuit 111 may be configured as an integrated circuit (IC) of one chip and may be configured by different chips.

The baseband circuit 111 is a baseband LSI or a baseband IC of one chip, for example. In addition, as shown by a broken line in FIG. 13, the baseband circuit 111 may include ICs of two chips of an IC 131 and an IC 132. In an example of FIG. 13, the IC 131 includes the DA converters 115 and 116 and the AD converters 117 and 118. The IC 132 includes the control circuit 112, the transmission processing circuit 113, and the reception processing circuit 114. A method of dividing configurations included in each IC is not limited thereto. In addition, the baseband circuit 111 may be configured by three or more ICs.

The control circuit 112 executes processing relating to communication with other terminals (including a base station). Specifically, the control circuit 112 handles MAC frames of three types of a data frame, a control frame, and a management frame and executes various processing defined in a MAC layer. In addition, the control circuit 112 may execute processing of upper layers (for example, a TCP/IP, a UDP/IP, and an application layer of an upper layer thereof) of the MAC layer.

The transmission processing circuit 113 receives the MAC frame from the control circuit 112. The transmission processing circuit 113 executes addition of a preamble and a PHY header to the MAC frame and encoding and modulation of the MAC frame. As a result, the transmission processing circuit 113 converts the MAC frame into a PHY packet.

The DA converters 115 and 116 execute DA conversion on the PHY packet output by the transmission processing circuit 113. In the example of FIG. 13, the DA converters are provided in two systems and execute parallel processing. However, only the DA converter may be provided or the DA converters may be provided by the number of antennas.

The RF circuit 121 is an RF analog IC or a high frequency IC of one chip, for example. The RF circuit 121 may be configured as one chip with the baseband circuit 111. Alternatively, the RF circuit 121 may be configured by two chips of an IC including a transmission circuit 122 and an IC including a reception processing circuit. The RF circuit 121 includes the transmission circuit 122 and a reception circuit 123.

The transmission circuit 122 executes analog signal processing on the PHY packet on which the DA conversion has been executed by the DA converters 115 and 116. An analog signal output by the transmission circuit 122 is transmitted wirelessly via an antenna. The transmission circuit 122 includes a transmission filter, a mixer, and a power amplifier (PA).

The transmission filter extracts a signal of a desired band from a signal of the PHY packet on which the DA conversion has been executed by the DA converters 115 and 116. The mixer up-converts a signal after filtering by the transmission filter into a radio frequency, using a signal of a constant frequency supplied from an oscillation device. The preamble amplifies a signal after the up-conversion. A signal after the amplification is supplied to the antenna and a radio signal is transmitted.

The reception circuit 123 executes analog signal processing on a signal received by the antenna. A signal output by the reception circuit 123 is input to the AD converters 117 and 118. The reception circuit 123 includes a low noise amplifier (LNA), a mixer, and a reception filter.

The LNA amplifies the signal received by the antenna. The mixer down-converts the signal after the amplification into a baseband signal, using the signal of the constant frequency supplied from the oscillation device. The reception filter extracts a signal of a desired band from a signal after the down-conversion. The extracted signal is input to the AD converters 117 and 118.

The AD converters 117 and 118 execute AD conversion on an input signal from the reception circuit 123. In the example of FIG. 13, the AD converters are provided in two systems and execute parallel processing. However, only one AD converter may be provided or the AD converters may be provided by the number of antennas.

The wireless communication apparatus according to this embodiment includes the AD converters according to the ninth embodiment as the AD converters 117 and 118. Because high-precision AD conversion is enabled in the AD converter according to the fourth embodiment, reception processing of a radio signal having high reliability is enabled in the wireless communication apparatus according to this embodiment.

The reception processing circuit 114 receives the PHY packet on which the AD conversion has been executed by the AD converters 117 and 118. The reception processing circuit 114 executes demodulation and decoding of the PHY packet and removing of the preamble and the PHY header from the PHY packet. As a result, the reception processing circuit 114 converts the PHY packet into the MAC frame. A frame after processing by the reception processing circuit 114 is input to the control circuit 112.

In the example of FIG. 13, the DA converters 115 and 116 and the AD converters 117 and 118 are arranged in the baseband circuit 111. However, the DA converters 115 and 116 and the AD converters 117 and 118 may be configured to be arranged in the RF circuit 121.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

1. An amplifying circuit comprising: an input terminal to receive an input voltage; an output terminal to output an output voltage; a first operational amplifier including an inversion input terminal connected to a first node, a non-inversion input terminal, and an output terminal connected to a second node; a first input impedance element having one end connected to the input terminal and another end connected to the first node; a first feedback impedance element having one end connected to the first node and another end connected to the second node; a second operational amplifier including an inversion input terminal connected to a third node, a non-inversion input terminal, and an output terminal connected to a fourth node; a second input impedance element having one end connected to the input terminal and another end connected to the third node; a second feedback impedance element having one end connected to the third node and another end connected to the fourth node; a third feedback impedance element having one end connected to the first node and another end connected to the fourth node; and an adder to add an output voltage of the first operational amplifier and an output voltage of the second operational amplifier and outputs an added output voltage.
 2. The amplifying circuit according to claim 1, wherein the first input impedance element is a first sample-and-hold circuit to sample the input voltage, and the second input impedance element is a second sample-and-hold circuit to sample the input voltage.
 3. The amplifying circuit according to claim 1, wherein the first feedback impedance element, the second feedback impedance element, and the third feedback impedance element are capacitative elements.
 4. The amplifying circuit according to claim 1, wherein the adder includes a third operational amplifier including an inversion input terminal connected to a fifth node, a non-inversion input terminal, and an output terminal connected to the output terminal, a third input impedance element having one end connected to the second node and another end connected to the fifth node, a fourth input impedance element having one end connected to the fourth node and another end connected to the fifth node, and a fourth feedback impedance element having one end connected to the fifth node and another end connected to the output terminal.
 5. The amplifying circuit according to claim 1, further comprising: a fourth operational amplifier including an inversion input terminal connected to a sixth node, a non-inversion input terminal, and an output terminal connected to the output terminal; a fifth input impedance element having one end connected to the second node and another end connected to the sixth node; a sixth input impedance element having one end connected to the fourth node and another end connected to the sixth node; a fifth feedback impedance element having one end connected to the sixth node and another end connected to the output terminal; and a sixth feedback impedance element having one end connected to the fifth node and another end connected to the output terminal.
 6. The amplifying circuit according to claim 4, wherein the third input impedance element is a third sample-and-hold circuit to sample the output voltage of the first operational amplifier, and the fourth input impedance element is a fourth sample-and-hold circuit to sample the output voltage of the second operational amplifier.
 7. The amplifying circuit according to claim 4, wherein the fourth feedback impedance element is a capacitative element.
 8. The amplifying circuit according to claim 1, wherein the adder includes a third sample-and-hold circuit to sample the output voltage of the first operational amplifier, a first AD converter to execute AD conversion on a voltage held by the third sample-and-hold circuit, a fourth sample-and-hold circuit to sample the output voltage of the second operational amplifier, a second AD converter to execute AD conversion on a voltage held by the fourth sample-and-hold circuit, and a digital adder to add output signals of the first AD converter and the second AD converter.
 9. The amplifying circuit according to claim 1, wherein the adder includes a buffer circuit to invert the output voltage of the first operational amplifier and outputs the output voltage, and a fifth sample-and-hold circuit to sample the output voltage of the second operational amplifier and the output voltage of the buffer circuit.
 10. The amplifying circuit according to claim 9, wherein the amplifying circuit has a differential configuration.
 11. An AD converter comprising the amplifying circuit according to claim
 1. 12. An integrated circuit comprising the AD converter according to claim
 11. 13. A wireless communication apparatus comprising the integrated circuit according to claim
 12. 